LTC4268IDKD-1#PBF【PDF 24/46 页】IC PD HIGH POWER W/CNTRL 32-DFN

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LTC4268-1

42681fc

Power Good Interface

The LTC4268-1 provides complimentary power good

signals to simplify the DC/DC converter interface. Using

the power good signal to delay converter operation until

the load capacitor is fully charged is recommended as this

will help ensure trouble free start-up.

The active high PWRGD pin is controlled by an open col-

lector transistor referenced to V

NEG

while the active low

PWRGD pin is controlled by a high voltage, open-drain

MOSFET referenced to V

PORTN

. The PWRGD pin is de-

signed to interface directly to the UVLO pin with the aid

of a pull-up resistor to Vcc. An example interface circuit

is shown in Figure 11.

the pin voltage and thus creating hysteresis. As the pin

voltage drops below this threshold, the current is disabled,

further dropping the UVLO pin voltage. If not used, the

UVLO pin can be disabled by tying to V

Shutdown Interface

To disable the 25k signature resistor, connect SHDN to

the V

PORTP

pin. Alternately, the SHDN pin can be driven

high with respect to V

PORTN

. Examples of interface circuits

that disable the signature and all LTC4268-1 functions are

shown in Figure 10, options 2 and 4. Note that the SHDN

input resistance

is relatively large and the threshold volt-

age is fairly low. Because of high voltages present on the

printed circuit board, leakage currents from the V

PORTP

could inadvertently pull SHDN high. To ensure trouble-free

operation, use high voltage layout techniques in the vicinity

of SHDN. If unused, connect SHDN directly to V

PORTN

Load Capacitor

The IEEE 802.3af specification requires that the PD maintain

a minimum load capacitance of 5礔. It is permissible to

have a much larger load capacitor and the LTC4268-1 can

charge very large load capacitors before thermal issues

become a problem. However, the load capacitor must not

be too large or the PD design may violate IEEE 802.3af

requirements. If the load capacitor is too large, there can

be a problem with inadvertent power shutdown by the PSE.

For example, if the PSE is running at 57V (IEEE 802.3af

maximum allowed) and the PD is detected and powered

up, the load capacitor will be charged to nearly 57V. If

for some reason the PSE voltage is suddenly reduced to

44V (IEEE 802.3af minimum allowed), the input bridge

will reverse bias and the PD power will be supplied by the

load capacitor. Depending on the

size of the load capacitor

and the DC load of the PD, the PD will not draw any power

from the PSE for a period of time. If this period of time

exceeds the IEEE 802.3af 300ms disconnect delay, the

PSE will remove power from the PD. For this reason, it

is necessary to evaluate the load current and capacitance

to ensure that inadvertent shutdown cannot occur. Refer

also to Thermal Protection in this data sheet for further

discussion on load capacitor selection.

applicaTions inForMaTion

PORTP

PWRGD

54V

42681 F11

PSE

LTC4268-1

ACTIVE-HIGH ENABLE

PORTN

UVLO

100k

Figure 11. Power Good Interface Example

Port Voltage Lockout

PoE applications require the PD interface to turn on below

42V and turn off above 30V. The LTC4268-1 includes an

internal port voltage lockout circuit to implement this basic

chip on/off control. Additionally, the LTC4268-1 includes

an enable/lockout function for the DC/DC converter that

is controlled by the UVLO pin and is intended to be driven

by PWRGD to ensure proper start-up. (Refer to Power

Good Interface.) Users have the ability to implement

higher turn-on voltages if necessary by connecting the

UVLO pin to an external resistive divider between V

PORTP

and V

PORTN

. The UVLO pin also includes a bias current

allowing implementation of hysteresis. When UVLO is

below 1.24V, gate drivers are disabled and the converter

sits idle. When the pin rises above the lockout threshold

a small current is sourced out of the UVLO pin, increasing

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